1. Field of the Invention
The present invention relates to improvement in circuit simulation accuracy and, more particularly, to a circuit simulation apparatus incorporating diffusion length dependence of MOS transistors, having not been considered so far, and to a method for creating a transistor model.
2. Description of the Related Art
As MOS transistors are being miniaturized in the development of semiconductors, simulation accuracy of a circuit simulator typified by SPICE is requested to be improved further.
FIG. 1 is a block diagram showing the configuration of a conventional circuit simulation apparatus. A simulation executing unit 1 is the main body of the simulator typified by SPICE and is actually a simulation executing program running on a computer. The simulation executing unit 1 reads a circuit net list 3 in which the connection descriptions of a circuit to be simulated are stored and calculates changes in the current and voltage of the circuit to be simulated, by referring to a transistor model 2 of MOS transistors.
For higher simulation accuracy, a transistor model is absolutely required to have higher accuracy. For higher accuracy of the transistor model, methods for extracting model parameters, such as threshold voltage, narrow-channel effect coefficient, short-channel effect coefficient, mobility and carrier speed saturation voltage, have been improved (for example, refer to FIG. 1 in Japanese Unexamined Patent Publication No. 2001-035930).
In addition, in creation of the BSIM3 and BSIM4 transistor models being famous as SPICE transistor models, in the case when device conditions are modified, a method for creating a transistor model in a short time by modifying extracted parameters into parameters corresponding to the changed conditions has been disclosed (for example, refer to FIG. 1 in Japanese Unexamined Patent Publication No. 2000-322456).
“However, in recent years, it has been pointed out by Gregory Scott et al. that the drain current of a MOS transistor changes depending on the diffusion length DL thereof, and this has attracted attention as a new factor for lowering simulation accuracy (“NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress” by Gregory Scott et al, IEDM Technical Digest, U.S.A., IEEE, 1999, IEDM-99, p. 827–830). In the case of transistors based on isolation technology, such as STI (Shallow Trench Isolation), as the isolation between transistors becomes finer, it is assumed that the mobility in the channel region under the gate electrode changes under the influence of crystal strain induced in the diffusion layer and the channel region owing to the existence of the isolation regions in the circumference, thereby resulting in the change in drain current.”
FIG. 2A is a plan view of an N-channel MOS transistor, and FIG. 2B is a sectional view taken along line II—II of FIG. 2A. As shown in FIG. 2A, the diffusion length DL designates the length of a field pattern 31 representing the diffusion layer and the boundary between the channel formation region and the isolation region by STI in a direction perpendicular to a gate electrode 32. The length corresponds to the total length of the source length, channel length and drain length. In FIG. 2B, numeral 41 designates a silicon substrate, numeral 42 designates a P-type well, numeral 43 designates an N-type source-drain region, numeral 44 designates an N-type LDD (Lightly Doped Drain) region, numeral 45 designates a gate insulating film, numeral 46 designates a gate electrode, numeral 47 designates an STI region, and numeral 48 designates an insulating film. The STI region 47 is formed by filling a trench dug into the surface of the silicon substrate 41 with insulating material and makes contact with the N-type source-drain region. In FIGS. 2A and 2B, an N-channel MOS transistor is shown. A P-channel MOS transistor has a similar structure that is obtained only when an N-type impurity is replaced with a P-type impurity.
However, the dependence of the drain current on the diffusion length DL is not incorporated in the transistor model 2, such as the BSIM3 and BSIM4 transistor models, for use in the present circuit simulation apparatus. In other words, as shown in FIG. 3 by the diffusion length dependence of the drain current of the N-channel MOS transistor, when the diffusion length DL is small, the measurement value (black dot) of the drain current ID is small. However, in the present MOS transistor model, as indicated by the straight line L0, the value of the drain current ID is constant which is obtained when the diffusion length of the transistor used for model parameter extraction is DL0. Hence, in the present circuit simulation apparatus typified by SPICE, simulation is carried out regardless of the presence of the DL dependence. This is a factor that impairs improvement in simulation accuracy.
Even in the case when the present circuit simulation apparatus not incorporating the diffusion length dependence is used, by creating many kinds of transistor models through parameter extraction for individual MOS transistors having different diffusion lengths DL beforehand, by selecting a transistor model having diffusion length DL and used for a circuit to be simulated from among the many kinds of models, and by using the selected transistor model, the accuracy of the simulation can be improved. However, since many kinds of transistor models having different diffusion lengths DL are created, a long time is required for parameter extraction and parameter fitting. In addition, MOS transistor models must be used selectively depending on the diffusion length DL during simulation. This proves complicated and human errors are apt to occur.